Nonvolatile flash memory devices store information in the form of charge in a flash memory cell. A flash memory cell has a CMOS transistor with an additional floating metal gate between the substrate and the transistors gate. The charge is stored in the floating gate and is injected to the floating gate during an operation known as programming. The charge may be removed during an operation known as an erase operation.
As the charge in the floating gate may vary contiguously, it is possible to store more than just one bit per flash transistor by using several charge levels to symbolize different sequences of bits.
FIG. 1 demonstrates a voltage level distribution for a 3 bpc (bits per cell) flash memory cell. The voltage level distribution includes eight lobes 101-108. Each lobe represents a 3-bit value.
The voltage level distributions of FIG. 1 illustrates non-overlapping lobes, however this is only schematic, and in practical cases the lobes may overlap. The reason for overlapping may be intentional for obtaining high programming speed, or due to the retention effect. For floating gate devices, an “old” page, may introduce greater overlap between lobes than a new page, since after many program/erase (P/E) cycles there is accumulated trap charge, which is de-trapped over time. After a long duration, every lobe may have a larger standard deviation (std) and may have a different mean location. These effects are also known as retention.
The 3 bpc cell includes a most significant bit (MSB), a central significant bit (CSB) and a least significant bit (LSB). A physical page of flash memory module may store three logical pages. This physical page is programmed one logical page after the other. The programming includes various types of programming such as MSB programming (in which some of the cells are programmed to a single lobe and some are left in the erase state. At the end of this programming process only two lobes exists, the erase and the MSB lobes), a CSB programming (in which the erase lobe and the MSB lobe are each split into two lobes by further programming pulses, depending on the original state of each cell and the corresponding CSB bit. At the end of this step there are four lobes.) and a LSB programming (in which each of the four lobes is further split to create 8 lobes, overall). The logical pages are read by applying various types of read operations such as MSB read (in which a MSB threshold 114 is used), CSB read (in which two CSB thresholds 112 and 116 are used) and LSB read (in which four LSB thresholds 111, 113, 115 and 117 are used). FIG. 2 shows similar distributions for the case of 2 bpc devices.
A NAND Flash array (or block) is constructed from NAND Flash memory cells. The NAND Flash memory cells are grouped into columns (or strings). FIG. 3 shows a typical prior art portion 30 of a NAND flash memory array that includes thirty two lines (wordlines 31(1)-32(32)) and multiple (Q) columns (32(1)-32(Q). Once column 32(q) is illustrated in further details—it shows the thirty two flash memory cells 34(q) of the column, bit line select transistor and gound select transistor, and the voltages 33(q) supplied to the transistors and flash memory cells (Bit Line Select, Vbias, Vth). Column 32(q) is connected to sense amplifier 35(q), that in turn is connected to latch 36(q). A string (column) is duplicated many times (for example Q=34560 times) in a block and includes several (for example—thirty two) flash memory cells. Each of the flash memory cells is associated with a different wordline (or row) which connects all of the corresponding cells in the other strings of the block. When a block is chosen, each string is connected to a corresponding bitline by turning on the Bit Line Select and the Ground Select transistors. When a read operation is performed, a sense amplifier is connected to the bit-line and after allowing some time (say 25 uS) for the bit-line voltage to settle, the result is stored by a latch.
In order to measure the charge in a certain cell within a string, all other cells are switched on by applying a high voltage on their gates (given by Vbias) and a comparison voltage, Vth, is applied to the gate of the selected cell. If the cell is charged and Vth is not high enough, the gate will not allow current to flow and the sense-amplifier will output a “0”. On the other hand, if the cell is not charge or Vth is high enough, current will flow and the sense-amplifier will output a “1”. Different schemes may exist where the cell being samples is biased with a constant voltage (say Vcc) but in the sense-amplifier a comparison against a reference string is performed which reference value may be determined by some external voltage, Vth.
The above sampling technique holds when a bit may be obtained only through a single threshold comparison. When more than a single threshold comparison is required, the above procedure may be performed for each threshold and the results may then be combined. Alternatively, several sense-amplifiers may be used simultaneously, each one compares against a different threshold, and the results are then combined to yield the required bit value.
All cells in a wordline (physical page) are programmed simultaneously and read simultaneously. In case of MLC or TLC, the programming of a wordline is divided into two or three stages, referred to as MSB, CSB and LSB page programming stages.
Due to manufacturing defects, some of the columns may not operate properly. In that case, NAND manufacturers, allocate spare strings which are used to replace the defective strings. The replacement is done during the manufacturing process, where the bad columns are detected and internal circuitry is used to remap the spare strings to replace. Typically, the replacement is not very efficient as entire bytes or words (16 bits) are replaced even if a single column was bad. That is, the columns are divided into chunks of 8 or 16 columns and the replacement is done on an entire chunk.
Alternatively, some manufacturers do not replace the bad columns and leave the task to the memory controller that controls the NAND Flash. That is, more strings are allocated on a NAND array to allow some spare strings for replacement. However, the re placements is not done at the NAND array level but rather, bad columns are handled by the controller instead.